1) Field of the Invention
The present invention relates to a large scale, low power consumption associative memory.
2) Description of the Related Art
In ordinary memories, read or write of data is performed by specifying an address. On the other hand, the associative memories have a function for searching and outputting data agreeing with or similar to input search data. The associative memories are also referred to as content addressable storages. The associative memories include a plurality of associative memory cells are connected to each of a plurality of match lines (agreement detection line). As a result of such a configuration, it becomes possible in the associative memories to execute data search simultaneously in all match lines.
When data search is to be executed, it is necessary to pre-charge the potential of all the match lines to a relatively high (hereinafter, “H”) level. If the result of the search shows that the data (hereinafter, “retention data”) retained in each of the connected associative memory cell agrees with the data to be searched (hereinafter, “search data”), the potential of the respective match lines is maintained at the H level. On the other hand, if there is a disagreement between the retention data and the search data for even one associative memory cell, the potential of the corresponding match line is reduced to a relatively low (hereinafter, “L”) level.
Suppose that due to a current search potential of many match lines is reduced to the L level. In order to perform the next search, these match lines are necessary to be pre-charged to the H level. However, there is a disadvantage that a lot of power is consumed in order to pre-charge these match lines from L level to H level.
Various proposals have been heretofore made for reducing power consumption in the associative memory. For example, Japanese Patent Application Laid-Open No. S62-293596 discloses an associative memory in which one word is formed of n bits, comprising a decoder that selects a word for writing n-bit data, a first associative memory cell array in which one word is formed of m bits, a first sense amplifier that detects the comparison result in the first associative memory cell array, a second associative memory cell array in which one word for performing comparison operation by using the output of the first sense amplifier is designated as (n-m) bits, and a second sense amplifier that detects the comparison result of the second associative memory cell array, corresponding to the output of the first sense amplifier.
According to this conventional art, power consumption is reduced since the second associative memory cell array and the second sense amplifier are operated only for the word that has agreed in the first associative memory cell array. However, when the memory capacity of the associative memory increases like nowadays, and the number of match lines becomes several tens times as many as that of at the time of filing this application, for example, 8 k (k=1024), power consumption required for pre-charge of the match lines is considerably larger than the power consumption by the sense amplifier, and hence the power consumption cannot be sufficiently reduced. It is an object of the present invention to provide an associative memory that operates in a large scale and at low power consumption.